Clik here to view.
Calling C Code (Uses OpenMP) from Python
Hello all,I'm a high school student working on running some Python code. It's a huge computational task so we actually have to run it on the Stampede super computer to make sure it completes in time....
View ArticleNew white paper: in-place multithreaded transposition with common code for...
A few months ago I posted about issues with producing a matrix transposition code that works well on Xeon Phi. Since then, I did more homework and improved the code to yield a satisfactory 113 GB/s...
View ArticleClik here to view.
dgemm: very slow with rectangular matrices
I need to calculate the products of some relatively small matrices. I've written a test program (attached, hopefully) which demonstrates several performance problems with MKL's dgemm function on Phi....
View ArticleHow To Froce a Kernel Dump
Hi,I have been working on MIC kernel modules and had kernel crash dump working for a while. After upgrading MPSS to mpss_gold_update_3, somehow the vmcore can no longer be generated. Does anyone know a...
View ArticleWhere can I get "intelr-xeon-phitm-pmu-rev1.01.pdf"
I get a manual of "intelr-xeon-phitm-pmu-rev1.01.pdf", but it's too old.I hope I can get a update one.Any help will be appreciated.
View Articleforwarding technique
Hi, I have a question on the pipeline of Xeon Phi. That is, does the pipeline of Xeon Phi support forwarding technique? If it does, there should not be any stalls for the RAW instructions (suppose the...
View Articleraw latency
Hi, In the SDG of Xeon Phi, it says the access time of L1 and L2 cache in terms of 'raw latency'. It is 1 cycle for the L1 cache and 11 cycles for the L2 cache. I wonder what does the 'raw latency'...
View ArticleMemory bandwidth measurement
I want to know the rate of memory bandwidth, in GNU/Linux, but i can't find some way.There are tools that read Memory bandwidth, but i believe they read the factory value no the current rate in time...
View ArticleCouldn'nt update micflash
I update the mic flash, but it failed.Any help will be appreciated.[root@supermicro mpss_gold_update_3]# /opt/intel/mic/bin/micflash -update /opt/intel/mic/flash/EXT_HP2_SMC_Bootloader_1_8_4326.css_ab...
View Articlewrong offload tag code
Hi,in the document listed here (the documentation for the latest intel fortran compiler 13.1.3)http://software.intel.com/en-us/node/413108#30B8C09D-9EC7-401B-8CFC-E4FC...the code listed after...
View Articlewrong offload wait/transfer example code
Hi,In this document http://software.intel.com/en-us/node/413108#30B8C09D-9EC7-401B-8CFC-E4FC...the code listed as example after thisThe following example demonstrates using the OFFLOAD directive, as...
View ArticleError: Engine_connect for an offloading code - SCIF problems
Hi there,A user of ours is building a pre-release version of NAMD that includes Phi offloading support but when we try and run it it claims it cannot find the Phi cards. I've also replicated the...
View ArticleParallelising this algorithm for MIC: Stuck!
Hello.This is also and OpenMP question.I'm trying to parallelise this algorithm for the MIC. It does cubic spline interpolation of SourceNum*Ni number of vectors of length Nj. So the interpolation is...
View ArticleMicctl not seeing card
All,Having trouble getting the mic drivers working.Running CentOS 6.4 with the 2.6.32-358.6.2.el6.x86_64 kernel (this is because we use Lustre as well).I am able to compile and install the kernel...
View ArticleIntegrated Memory Controller device missing in Linux running on Xeon e5-2648L
Hi,I like to enquire on Integrated Memory Controllers on Xeon e5-2648L.Require the information for linux edac driver implementation on my Intel Sandy Bridge for checking Memory Errors.1)As in processor...
View ArticleChange default /tmp/coi_procs location? (COI_PROCS_DIR)
Hi there,Our Intel Xeon Phi cards are in diskless compute nodes in our IBM iDataplex cluster and we have an issue where /tmp gets filled up due to files being left behind in the /tmp/coi_procs...
View ArticleECC memory percentage?
Hello,I am looking for the percentage of GDDR5 memory used when ECC is activated on Xeon Phi to check that the result of micinfo (GDDR Size) is correct.I've read 12.5% (1 bit per byte), 3.125%, and...
View ArticleHow to abort application once error encountered in offloaded section
Hi,I am having a C parallel code. In this code there is a offload section using Cilk. Memory is being asigned in shared function. I want this application get aborted gracefully when error is...
View ArticleHow to allocate shared 2D Array
Hi,I am trying to allocate 2D array, below is code for the same. It is compiling with some warning but is giving run time error. Please let me know the error in code and how to succefully allocate 2D...
View ArticlePorting __m128i instructions to Phi
I have a very complex project which has being heavily optimized to take advantage of SSSE2 and SSSE3 instructions. For example in my project I have the following defines: #define ADDS8(a, b)...
View Article