Using L1/L2 cache as a scratchpad memory

Dear all,

Explicitly cache control is a one of important feature in Xeonphi (MIC). How could I use the L1 or L2 as scratchpad memory and also sharing them data between the cores?

In addition,  is there any way to hack the MESI state of the cache line in the distributed tag directory (DTD)? 

Thanks in advance.

Regards