Please urgent. How memory paging are assigned to CPU cache sets
Hi I’m looking at how memory pages are assigned to CPU cache sets. I know that RAM blocks are assigned to certain lines in CPU cache sets. So, I want to the mechanism to map pages to the cache. For...
View ArticleIntel MPI support for symmetric mode on Windows
Is there any support for running in symmetric mode on windows using Intel MPI? I notice that there are no mic headers/libraries included in version 4.1 which makes me believe the answer is no. Is...
View ArticleNFS micuser setup with internal bridge?
Hi All,I've setup an NFS as describe in section 7.4 of the MPSS user's guide (mpss 3.2.3); however, I have the cards mount /home on the host, so that all mic cards see the appropriate user directory...
View ArticleWhy it is so difficult to write AVX code on MIC!
Hello,I am writing an AVX code to calculate the complex multiplication. The code is listed below, 1 typedef std::complex<float> Value; 2 void Benchmark::gridKernel(const int support, 3...
View ArticleAccessing Local Resource of other KCN
Hi,Recall Figure 2-12 (Host and Intel® MIC Architecture Physical Memory Map) on in the Intel Xeon Phi Systems Software Developers Guide.The low memory (0 - 512G) is divided into 8x64GB blocks where...
View ArticleHow to further optimize?
Hello everyone,I have started overcoming the performance issues that I described in a previous thread (https://software.intel.com/en-us/forums/topic/516335). As suggested there, I enabled reports for...
View Articlevector/parallel optimization
I've posted my examples based on netlib vectors benchmark at https://github.com/tprince/lcdThese demonstrate how to optimize vectorization (and, where appropriate, parallelization) for MIC (native) and...
View ArticleUnable to use boost::bind with intel MIC in a function with comparison operators
HiI am using a test program for compiling a boost::bind in intel MIC. Here are the details of the code and platform on which it is compiled. I am using thread building blocks in my code, but the...
View ArticlePossible compiler bug in compiling code for MIC (XE SP1 Update3)
Hi, I had logged a similar query here https://software.intel.com/en-us/forums/topic/517612With reference to the code below, it looks like a possible compiler bug in compile code for intel MIC...
View ArticleCompiler bug with target attribute in icc 14
Hi there,I'll just let the code and output speak for itself:// broken #define DECLARE_OFFLOADED __attribute__ ((target (mic))) // working //#define DECLARE_OFFLOADED typedef void (init_t) (void);...
View ArticleCompile on machine without a MIC card for MPSS 3.2.3
I have seen a few posts about this, but they seem out of date so I am asking afresh . . . .I am trying to compile on a mchine that does not have a MIC card (its part of a cluster where the MICs are on...
View ArticleMKL versus OpenMP
It appears that MKL is not optimized for the MIC and is much slower than on the CPU. Performing the computation C=A*A' (A is oblong, many more cols than rows. Stored as nrows*ncols sized vector) with...
View ArticleCorrectly profiling MPI application on the MIC (separate results for each...
Dear all,Following the instructions here https://software.intel.com/en-us/forums/topic/358774 I have been able to profile my MPI application on the MIC, however the results are not collected exactly...
View ArticleUsage of _mm512_mask_prefetch_i32gather_ps for doubles
Dear all,I want to implement prefetching for sparse complex double precision data using Intrinsics.A linear array contains the indexes of the sparse complex double elements like so...
View Articlelibntl for KNC
Does anyone know if it is possible to port the Number Theory Library (NTL) on the Phi?Thanks in advance, Tasos K.
View ArticleKnights Landing will not be a coprocessor but a many core processor?
I read this from online."Intel's Knights Landing would be available as either a PCIe-based add-in board or as a socketed, bootable, x86-compatible processor based on the Silvermont architecture." So...
View ArticleLDAP configuration problems
Dear all,I have a node with two Xeon Phi (mic0 and mic1). I have configured the LDAP support by the Intel manual: https://software.intel.com/en-us/articles/setting-up-ldap-support-for-in...The...
View ArticleGenery query on system setup support
Greetings,Don't know if this is the right forum to get some advice and tips on system type setup queries relating to MPSS software.I can provide more specific details in a separate post if...
View ArticleVectorization Lab Fortran Problem
Hi,i downloaded Intel Vectorization Lab Session (Fortran Version) and i have a problem compiling example of elemental function (file: vectorization_elem_funct_directive.f90).I receive this...
View ArticleCompile error on the offload mode.
Hi~ all, I met some problems when I transform my codes from non-offload mode to offload mode.The command I used to compile the codes is: icc -std=c++0x -openmp -O3 -vec-report=3The compiler I used is...
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